A 1GHz Fractional-N PLL Clock Generator with Low-OSR ΔΣ Modulation and FIR-Embedded Noise Filtering

Offering less than 1ppm frequency resolution, a ΔΣ fractional-N PLL enables flexible frequency planning and reliable spread spectrum modulation for digital clock generation [1, 2]. Use of low-cost ring VCOs however, mandates a wideband PLL design, which makes it difficult for the PLL to filter out high-frequency quantization noise from the ΔΣ modulator. In many digital clocking systems, such as serial links and microprocessors, short-term jitter is as important as long-term jitter. Hence, when high-frequency quantization noise is not sufficiently suppressed by the PLL it can easily degrade the overall system performance. This paper describes a noise filtering method for quantization noise reduction that is not sensitive to PVT variations. The resulting fractional-N PLL clock generator is the first one demonstrated with an oversampling ratio (OSR) of about 10, where the OSR is defined by fref/(2fbw) in this work.